This relates to integrated circuits and, more particularly, to programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements on a programmable integrated circuit to configure the device to perform the functions of the custom logic circuit.
Configuration data may be supplied to a programmable device in the form of a configuration bit stream. After a first configuration bit stream has been loaded onto a programmable device, the programmable device may be reconfigured by loading a different configuration bit stream in a process known as reconfiguration. An entire set of configuration data is often loaded during reconfiguration.
Programmable devices may be used for coprocessing in big-data or fast-data applications. For example, programmable devices may be used in application acceleration tasks in a datacenter and may be reprogrammed during datacenter operation to perform different tasks. However, the speed of reconfiguration of programmable devices is traditionally several orders of magnitude slower than the desired rate of virtualization in datacenters. Moreover, on-chip caching or buffering of pre-fetched configuration bit-streams to hide the latency of reconfiguration is undesirably expensive in terms of silicon real estate. Additionally, repeated fetching of configuration bit-streams from off-chip storage via the entire configuration circuit chain is energy intensive.
Situations frequently arise where it would be desirable to design and implement programmable devices with off-chip memory that enables improved reconfiguration speed and reduced energy consumption.
It is within this context that the embodiments herein arise.